Huawei has released comprehensive details on the second iteration of its Tau (τ ) Scaling Law, outlining a technological roadmap that relies heavily on a novel 3D packaging technique called LogicFolding. Disclosed on July 3, 2026, the “Time Scaling Theory for Multi-Level Electronic Systems V2” paper provides concrete implementation insights and performance data, demonstrating how Huawei intends to bypass traditional constraints imposed by Moore’s Law. Crucially, the roadmap extends the application of LogicFolding beyond mobile processors and directly into its enterprise-grade Ascend AI accelerators by the end of the decade.
According to TrendForce, the upcoming Kirin 2026 mobile processor will serve as the first real-world validation platform for this dual-layer LogicFolding architecture. The paper reveals that the Kirin 2026 achieves a transistor density of 238 million transistors per square millimeter (MTr/mm²), a 53.5 percent increase over the 155 MTr/mm² baseline of the 2025 Kirin 9030 Pro. Huawei claims that achieving a comparable density gain through conventional geometric node scaling would typically require approximately three years of development.
The Mechanics of LogicFolding Technology
LogicFolding is a sophisticated methodology that partitions digital, analog, and memory circuits across vertically stacked active silicon tiers. By stacking these components rather than placing them side-by-side on a single plane, Huawei can drastically reduce the chip’s physical footprint while shortening the interconnect distances between critical components. The company notes that on a mobile system-on-chip (SoC), LogicFolding delivers a 55 percent stepwise increase in transistor density and a 41 percent reduction in power consumption at equivalent performance levels on a fixed manufacturing node.
The V2 paper projects that this technology will evolve from localized critical-path optimization to full multi-layer architectures over the next decade, with future packages integrating three or more active layers. This shift is enabled by advancements in low-temperature hybrid bonding, which mitigates the severe thermal constraints typically associated with stacking active logic layers. The paper also notes that TSV (through-silicon via) landing point migration from upper metals to M6 frees over 30 percent of routing resources, further improving performance. Under this trajectory, Huawei projects that transistor density will scale toward 400 MTr/mm² and beyond between 2026 and 2035.
The significance of this roadmap cannot be overstated in the context of US export controls. Because LogicFolding is a packaging and architecture innovation rather than a lithography advancement, it does not require the extreme ultraviolet (EUV) machines that are currently restricted by Western export controls. Huawei is effectively building a parallel scaling pathway that sidesteps the conventional lithography bottleneck, potentially allowing it to achieve competitive performance without access to TSMC or ASML’s most advanced tools.
(Related: Huawei Unveils Chip Breakthrough, Targets 1.4nm Chip Density by 2031)
Scaling to Ascend AI Accelerators by 2030
While the immediate application of LogicFolding is in consumer smartphones, with the first Kirin 2026 device expected this fall, the strategic endgame lies in data center AI infrastructure. The Tau Law V2 paper explicitly identifies Huawei’s Ascend AI chips as the next major application for this technology, projecting integration into the Ascend 990 AI accelerator around 2030. The report notes that 3D folding is expected to become the primary carrier of Huawei’s architecture through 2035.
In the context of AI system design, Huawei envisions a co-designed stack that combines a memory-semantic Unified Bus fabric, near-package optical I/O, and edge-to-surface 3D folding. The company projects that this integrated approach will deliver more than a 100-fold growth in hardware integration by 2035. Nvidia CEO Jensen Huang recently acknowledged the Tau Scaling Law as a “breakthrough,” underscoring the global significance of Huawei’s alternative scaling strategy. The first Kirin 2026 smartphone is expected to debut this fall, providing the market with its first concrete benchmark of LogicFolding’s real-world performance and setting the stage for the technology’s eventual migration into the AI data center.
The broader strategic implication of the Tau Law V2 is that China is developing a credible, domestically controlled roadmap for semiconductor performance scaling that does not depend on Western-controlled lithography technology. This is a significant development for the global technology competition. For years, the prevailing assumption among US policymakers was that restricting China’s access to EUV machines and advanced foundry services would permanently cap the performance of Chinese chips.
The Tau Law V2 paper directly challenges that assumption, presenting a technically rigorous alternative pathway that could keep Huawei’s Ascend chips competitive with Western AI accelerators through the end of the decade, even without access to the most advanced manufacturing nodes.
The Tau Law V2 paper is also notable for its transparency. By publishing detailed technical specifications and performance projections, Huawei is making a deliberate statement to the global semiconductor community: that its alternative scaling roadmap is grounded in rigorous engineering rather than marketing claims.
Nvidia’s Jensen Huang’s acknowledgment that the Tau Scaling Law represents a genuine breakthrough lends external credibility to Huawei’s approach. Whether LogicFolding ultimately delivers on its projections will be determined by the Kirin 2026 launch later this year, but the publication of the V2 paper has already shifted the terms of the debate about China’s long-term semiconductor capabilities.
(Related: China’s Domestic AI Stack is Forcing a Rethink of Export Control Logic)