Huawei has moved its Ascend 960DT schedule forward to the first quarter of 2027 while setting out its most detailed public specifications yet for an up-to-4,096-NPU computing system. The announcement, made at Huawei Connect in Shanghai, couples the accelerated chip roadmap with the Atlas 960E SuperPoD, a tightly linked AI system that Huawei says is designed for much larger training and inference environments.
In its September 17 keynote, Huawei said Ascend 960DT would be available three quarters ahead of its original roadmap, with Ascend 960PR slated for the third quarter of 2027, one quarter ahead of schedule. The company also laid out plans for Ascend 970 in 2028 and Ascend 980 in 2029. The key point is timing rather than a current shipment: Huawei presented 2027 as a roadmap target, not as evidence that Ascend 960DT systems are already in customer deployment.
Reuters independently reported the Q1 and Q3 2027 dates and Huawei’s plan to link systems at far larger scale. Its report placed the announcement in the context of Huawei’s effort to expand domestic AI-computing options as Chinese demand for training and inference capacity rises.
A roadmap that shifts from single processors to integrated systems
The Ascend 960DT is a processor on Huawei’s announced roadmap. The Atlas 960E SuperPoD is the larger system built around Ascend 960 chips, optical interconnect, memory, storage, and management components. Keeping those two levels separate matters. A processor availability target does not establish that the full 4,096-NPU configuration has been deployed, and a system specification is not a directly comparable benchmark for an individual accelerator.
Huawei describes a SuperPoD as a collection of computing nodes tightly coupled through high-speed interconnect and unified memory addressing so that they can function more like one logical computer. That architecture is central to the company’s answer to a scaling problem: simply adding more conventional servers increases the amount of time models spend moving data among machines. Huawei said that, at clusters approaching 100,000 NPUs, intra-cluster communication can account for more than 40% of training time.
The company says its own Markov Lab simulated a 2.75-times improvement in Model FLOPs Utilization for a 100,000-NPU cluster built from 4,000-NPU SuperPoDs instead of eight-NPU servers. That is a Huawei simulation, not an independent benchmark, but it makes the product argument clear. Huawei is selling architecture and interconnect as much as raw chip performance. The same emphasis appeared in EastFrontier’s recent coverage of Huawei’s 7.2T optical link for future China AI clusters, where networking capacity was positioned as a limiting factor in domestic AI scale-up.
Atlas 960E places optics, memory, and power at the center
Huawei says a single Atlas 960E SuperPoD can scale to up to 4,096 NPUs, with 8 EFLOPS of FP8 compute performance and up to 1 petabyte of HBM capacity. Those are maximum Huawei specifications, not measured application throughput. The company calls the system the industry’s first near-packaged-optics, or NPO, SuperPoD, using an interconnect product it calls Hi-ONE alongside its UnifiedBus architecture.
Hi-ONE is Huawei’s high-density optical-interconnect-node engine. The company says each engine supports 7.2 Tbit/s of transmission capacity. In the Atlas 960E design, Huawei says 5,500 Hi-ONE units replace the 48,000 conventional 800G optical modules that a comparable all-to-all connection would otherwise require. It says that change reduces power consumption by more than 550 kilowatts, doubles fault-free operating time, and produces 99.8% system availability.
These should be read as company design and reliability claims. Neither the keynote nor Reuters establishes independently audited power use, availability, or production yields. Still, the figures show why Huawei is emphasizing NPO. A training or inference cluster cannot grow indefinitely if each increment of compute requires a matching multiplication of optics, electrical power, and failure points. The new system seeks to move that constraint from a rack-level hardware problem to a more integrated optical-and-memory design.
Huawei’s announcement also adds a new product-level layer to the broader domestic-chip policy environment. China’s 2026 electronics plan put AI hardware at the center of its 2030 objectives. The Atlas 960E is not government policy, but it illustrates the type of high-density system Chinese suppliers are trying to build around locally developed processors.
UnifiedBus targets a million-NPU architectural ceiling
The most ambitious number in Huawei’s presentation was not 4,096. It was one million. Huawei says a two-tier, four-plane Clos network can connect up to 512,000 NPUs, while a multi-rail topology can support up to one million. Those are architecture ceilings, not a claim that Huawei has installed a million-NPU AI cluster.
Huawei framed UnifiedBus as the means to connect multiple subsystems with a single protocol and reduce conversion overhead between Ascend SuperPoDs, Kunpeng general-purpose SuperPoDs, and KV-cache storage. For long-context and agentic inference, it also introduced OceanStor M900 as a context-memory storage cluster. The company says the design is intended to give compute, general-purpose processing, and memory tiers direct single-hop access to the relevant KV-cache layer.
That architecture reveals a shift in the competitive question. Domestic accelerator programs are often assessed one chip at a time, usually through theoretical operations, memory bandwidth, or software compatibility. Huawei’s September 17 presentation instead asks whether a Chinese AI stack can coordinate processors, optics, storage, and software at cluster scale. The answer remains prospective: Ascend 960DT is a 2027 target, and the biggest system claims are Huawei’s own. But moving the timetable forward makes that prospective capacity relevant sooner for Chinese developers planning the next cycle of large-model infrastructure.