Nano-Core Chip, also known as NCC, has announced a 1 billion yuan C1 financing round to support its work on 3D computing-in-memory chips. The Hangzhou company says it is developing a 3D-CIM architecture that combines DRAM-based near-memory computing, SRAM computing-in-memory, and RISC-V heterogeneous computing. The round was reported by Zhidx on September 9 and confirmed in the company’s own announcement.
The financing places Nano-Core Chip in a crowded but strategically important part of China’s semiconductor market. Rather than compete only by designing a conventional GPU, the company is pursuing architectures intended to reduce the cost of moving data between memory and compute. That issue has become more important as AI models require larger datasets, longer contexts, and more memory bandwidth.
The technology remains early. Nano-Core Chip’s claims about density, energy efficiency, and commercialization are company claims or internal-test results, not independent product benchmarks. The new financing does, however, give the company resources to pursue a more difficult objective: turn a specialized architecture into chips, systems, software, and customer deployments.
A 1 Billion Yuan Round for 3D-CIM Architecture
Nano-Core Chip said the C1 round was worth 1 billion yuan. The named investors include Advantage Capital, Yuanhao Investment, GP Capital, Sunshine Life, Oriza Hua, Delian Capital, Kuanqiao Hengsong, Houxue Capital, Meig Smart, Hengxu Capital, and Huaqin Technology. Zhidx also reported that a large-model company participated, but did not identify it. That investor should not be guessed.
The company’s legal Chinese name is Hangzhou Micro-Nano Core Electronics Technology Co., Ltd. It uses the English name Nano-Core Chip, or NCC. The C1 designation indicates a later-stage financing step after earlier institutional backing, but the company did not disclose a post-money valuation or detailed ownership structure.
Funding is important in this segment because 3D memory and computing-in-memory designs require more than an algorithm or a software team. A chip company must fund architecture, verification, tape-out, packaging, software development, boards, systems, and customer evaluation. Each stage introduces technical and capital risk.
Chinese AI-chip startups have attracted large sums as cloud providers and AI developers seek alternatives to foreign accelerators. EastFrontier has followed that broader trend, including domestic GPU expansion as Chinese firms adjusted to chip restrictions. Nano-Core Chip is approaching the problem from a memory-centric angle rather than simply replicating a GPU path.
Why Memory Movement Matters for AI Chips
Many AI workloads are constrained not only by arithmetic capacity but also by the cost of fetching and moving data. Large models need repeated access to parameters, activations, and key-value caches. If the processor must repeatedly move data between separate memory and compute units, latency and energy use can become significant.
Nano-Core Chip says its 3D-CIM design combines three elements. The first is DRAM 3D near-memory computing. The second is SRAM computing-in-memory. The third is RISC-V heterogeneous computing. The company presents this combination as a way to align different memory technologies and programmable components around AI workloads.
The company says its architecture can improve compute density by four to six times and energy efficiency by five to ten times. These are not independent measurements, and they should be treated as company claims. The actual results will depend on workload, precision, memory configuration, software support, process technology, and how a finished system is used.
Computing-in-memory is attractive because it attempts to perform parts of calculation closer to where data resides. But making such designs commercially useful requires solving accuracy, programmability, manufacturing yield, thermal behavior, and integration with standard software stacks. A promising architecture does not automatically translate into a product that data-center operators can deploy at scale.
That is why Nano-Core Chip’s emphasis on RISC-V matters. A programmable control and orchestration layer may help make specialized memory-compute hardware easier to integrate. It also creates another engineering challenge: customers need compilers, runtimes, libraries, and tools that make the hardware useful without forcing teams to rewrite every application.
Commercial Proof Is the Next Hurdle
Nano-Core Chip says it is working toward mass commercialization in the near term. The company has not disclosed a production date, foundry partner, named customer, or independently verified performance result. Those omissions are normal for a young semiconductor company, but they define the questions that will determine whether the C1 round has lasting impact.
Investors will look for evidence that the company can move from architecture to repeatable hardware. That includes whether chips reach tape-out, whether systems can run common AI frameworks, whether customers can benchmark real inference or training tasks, and whether the hardware’s energy claims survive outside a controlled test environment.
The funding also arrives at a moment when China’s AI infrastructure strategy is becoming more explicit. Domestic chips are not valuable only as a geopolitical substitute; they need to offer workable economics for model developers and cloud providers. Nano-Core Chip’s bet is that memory-centered architectures can create that value.
EastFrontier’s earlier coverage of Moore Threads’ physical-AI training push illustrated how Chinese hardware firms are seeking specific AI workloads where their systems can gain traction. Nano-Core Chip is making a similar argument from a different technical starting point.
The 1 billion yuan round gives NCC time to make that argument in silicon. The decisive evidence will come after financing: chips, software, customer tests, production yields, and deployments. Until then, the company’s technical advantages remain a well-funded proposition rather than a proven market result.