Researchers at Peking University’s School of Integrated Circuits have unveiled a prototype electronic design automation (EDA) tool that takes a fundamentally different approach to chip design, and one that is directly compatible with Huawei Technologies’ newly announced LogicFolding semiconductor architecture. According to the South China Morning Post, the tool was announced on Tuesday and represents an important step toward reducing China’s dependence on Western EDA software, which currently dominates the global market through companies such as Synopsys and Cadence Design Systems.
EDA software is the invisible but indispensable infrastructure of the semiconductor industry. Every chip designed in the world, from smartphone processors to AI accelerators, is created using EDA tools that translate engineering specifications into the precise geometric patterns etched onto silicon. The global EDA market is effectively a duopoly, with Synopsys and Cadence together controlling the vast majority of revenue. Both are US companies, and their software has historically been subject to export control considerations, making the development of credible domestic alternatives a strategic imperative for China’s semiconductor ambitions.
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The True-3D Design Methodology
The Peking University prototype distinguishes itself through what its developers describe as a “true-3D” approach to chip layout. Conventional EDA software designs chips layer by layer, optimizing each two-dimensional plane before stacking them, an approach analogous to designing a multi-story building one floor at a time without considering how the floors interact structurally. The PKU tool, instead, treats the entire multilayer chip as a single integrated structure from the outset, simultaneously optimizing the vertical stack to minimize signal travel distance and heat generation across all layers.
Early test results on open-source, industry-grade chip designs show a 30% reduction in total internal wire length compared with traditional EDA software, along with measurable improvements in performance and thermal management. Wire length is a critical metric in chip design because longer wires increase electrical resistance, slow signal propagation, and generate more heat, all of which degrade performance and energy efficiency. A 30% reduction in wire length at the design stage translates directly into faster, cooler, and more power-efficient chips at the manufacturing stage.
Alignment with Huawei’s Tau Scaling Law
The timing of the PKU announcement is closely linked to Huawei’s disclosure on Monday of its LogicFolding architecture and the associated Tau (τ) Scaling Law. Blocked from acquiring the advanced extreme ultraviolet (EUV) lithography machines needed to shrink transistors to sub-3nm dimensions, Huawei has pivoted its semiconductor strategy toward a different axis of improvement: speed. The Tau Scaling Law focuses on accelerating the propagation of electrical signals within a chip by reducing resistance and tightening internal wiring, rather than shrinking individual transistors.
LogicFolding is the physical implementation of this strategy, a three-dimensional chip architecture that stacks functional layers to reduce the distances signals must travel. The PKU EDA tool, by treating the chip as a single 3D structure during design, provides the software infrastructure needed to execute LogicFolding designs effectively. He Tingbo, chairwoman of the Huawei Scientist Committee and president of the company’s semiconductor business department, underscored the collaborative nature of the challenge at a media briefing on Monday: “If we look at the upcoming decade, no single company can address all these challenges alone.”
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The Road to 1.4nm Performance by 2031
Huawei has set an explicit target of producing chips by 2031 that match the performance of advanced 1.4-nanometer technology without relying on Western chipmaking tools. Achieving this goal requires simultaneous advances across multiple domains: chip architecture (LogicFolding), design software (the PKU EDA prototype), manufacturing processes (SMIC’s ongoing node development), and packaging technology (advanced 3D stacking). The PKU announcement suggests that China’s academic institutions are being mobilized as active participants in this industrial strategy, complementing the efforts of commercial chipmakers.
The development also carries implications for the broader EDA market. While the PKU prototype is at an early stage and would require years of development before it could serve as a production-grade replacement for Synopsys or Cadence tools, its existence signals that serious technical work is underway. For investors and policymakers tracking China’s semiconductor independence trajectory, the convergence of Huawei’s LogicFolding architecture and Peking University’s 3D EDA research represents a coherent, coordinated approach to a problem previously considered intractable.
China’s EDA development effort is not limited to Peking University. Empyrean Technology, a publicly listed Chinese EDA company, has been expanding its product portfolio for over a decade, and several university research groups have been working on specialized EDA tools for years. What distinguishes the PKU announcement is its explicit alignment with a commercial chip architecture, Huawei’s LogicFolding, that is currently under active development for production deployment. This alignment between academic research and industrial application is precisely the kind of coordination that China’s semiconductor strategy requires if it is to close the gap with Western EDA incumbents within the 2031 timeframe Huawei has set for its performance targets.