Huawei Unveils Chip Breakthrough, Targets 1.4nm Chip Density by 2031

Huawei has proposed a fundamental rethinking of how semiconductor progress can be achieved without access to the world’s most advanced lithography equipment. At the IEEE International Symposium on Circuits and Systems (ISCAS) 2026, the company unveiled two interconnected innovations: the Tau Scaling Law, a new theoretical framework for measuring chip performance gains, and LogicFolding, a 3D transistor stacking architecture designed to achieve 1.4 nm-equivalent transistor density by 2031.

A New Geometry for Chip Development

The keynote was delivered by He Tingbo, president of Huawei’s semiconductor business and director of its Scientist Committee. LogicFolding achieves its density targets by folding transistors vertically rather than continuing to shrink them horizontally, a method that circumvents the need for ASML’s extreme ultraviolet (EUV) lithography machines. Those machines, which are essential for producing chips below 5nm using conventional planar techniques, have been blocked from export to China since 2019 under pressure from the US government.

The Tau Scaling Law provides the theoretical underpinning for this approach, offering a new metric for measuring chip performance gains through 3D stacking rather than the traditional Moore’s Law framework of transistor count per unit area. Huawei is essentially arguing that vertical integration can substitute for the horizontal miniaturization that has defined semiconductor progress for decades. This is not merely an engineering claim, it is a strategic reframing of what “advanced” means in a world where geopolitical restrictions have severed access to the conventional path forward.

Building on SMIC’s 7nm Foundation

Huawei’s current generation of Kirin processors is manufactured by SMIC using its 7nm N+2 process, a node developed without EUV equipment through multi-patterning, a technique that uses multiple exposures of older deep ultraviolet (DUV) light sources to achieve finer features. This was the same process used in the Kirin 9000S chip that powered the Mate 60 Pro, the 2023 device whose existence shocked US officials and demonstrated that China had advanced further than expected despite export restrictions.

Huawei said it has already designed and mass-produced 381 chips over the past six years based on the Tau Scaling Law, for use in industries including smartphones and AI computing. The LogicFolding architecture represents the next step in that roadmap. By stacking transistor layers vertically, Huawei can increase effective density without requiring a new lithography node, buying time while domestic EUV alternatives are developed. The company has been investing heavily in its own semiconductor tooling ecosystem, and the Tau Scaling Law provides a framework for communicating progress to investors, partners, and policymakers in terms that do not depend on the conventional nm node nomenclature.

Ascend Chips Fill the Nvidia Vacuum

The announcement comes as Huawei is actively expanding the output of its Ascend AI chip line. US export controls have progressively eliminated Nvidia’s ability to sell its most advanced accelerators to Chinese customers, the H100 was banned in 2022, followed by the H800 and A800 in 2023, and the H20 in 2025. As a result, Chinese AI companies have been forced to turn to domestic alternatives. DeepSeek V4 has already been reported to run on Huawei chips, and the broader market shift is reflected in data showing that China’s domestic chipmakers have seized 41 percent of the local AI market as Nvidia’s grip loosens.

The Ascend 910C and its successors are increasingly being deployed in large-scale AI training clusters by Chinese tech companies, and Huawei’s ability to supply these chips at scale has become a critical factor in China’s AI development trajectory. The LogicFolding roadmap, if executed successfully, would give Huawei a credible path to producing AI accelerators that can compete with Nvidia’s next-generation products on performance metrics, rather than just serving as a stopgap alternative.

The Long Road to 1.4nm

Reaching 1.4nm-equivalent density by 2031 is an ambitious target that will require sustained investment and continued innovation in materials science, packaging, and chip design. The LogicFolding approach is not without challenges: 3D stacking introduces heat dissipation problems and increases manufacturing complexity. Yields on stacked chip architectures are typically lower than on planar designs, at least in the early stages of production, and the tooling required for precise vertical alignment adds cost and time to the manufacturing process.

However, the approach represents a credible path forward that does not depend on the geopolitical resolution of export control disputes. If Huawei succeeds, the implications extend well beyond the company itself. A domestically developed pathway to advanced chip density would significantly reduce China’s vulnerability to technology sanctions and could reshape the global semiconductor landscape in ways that current US policy has not fully anticipated.

What Success Would Mean for the Industry

The broader significance of the Tau Scaling Law and LogicFolding architecture extends beyond Huawei’s own product roadmap. If the approach proves viable at commercial scale, it would provide a blueprint that other Chinese chip designers could adopt, potentially enabling a generation of domestic AI accelerators that do not require EUV lithography. SMIC, which manufactures Huawei’s current chips, has been investing in its own 3D packaging and stacking capabilities, and a successful LogicFolding demonstration would accelerate that investment.

For US policymakers, the announcement presents a difficult challenge. Export controls on EUV machines and advanced chip designs were predicated on the assumption that these restrictions would create an insurmountable technical barrier. Huawei’s proposal suggests that the barrier may be navigable through architectural innovation, even if the path is longer and more expensive than the conventional route. The question is no longer whether China can develop advanced chips without Western equipment, but how long it will take and at what cost.