Shanghai’s software and information-services 15th Five-Year Plan, reported as issued August 11, sets two long-term sector goals for 2030 and outlines a push to connect locally made hardware with the most widely used model architectures. The plan targets a 4 trillion yuan software-and-information-services sector and 1.1 trillion yuan in value added by 2030, while calling for deeper integration of domestic chips with mainstream models.
It also highlights research directions in next-generation model architectures, physical intelligence, world models, quantum intelligence, and brain-inspired intelligence. The agenda was detailed in reporting by Cailian Press, which underscores the emphasis on full-stack capabilities that span compute, memory, interconnect, and deployment scale, and can be read in the Cailian Press report.
The document’s research roadmap places advanced model exploration alongside an explicit hardware strategy. It specifies integration across GPU and NPU, QPU, CPO, HBM, and heterogeneous servers, signaling intent to synchronize model development with the underlying compute substrates and data movement technologies. For readers tracking earlier market dynamics around the city’s artificial intelligence sector, EastFrontier has chronicled prior milestones in earlier AI industry growth. Within this new plan, the interplay between model research and infrastructure planning is presented as central to achieving the scale and value-added targets by 2030.
2030 Targets Tie Software Scale to AI Stack Integration
The plan’s 2030 goals are not just macro targets for sector size and value added. They also frame how software and information services will be built on, and enabled by, a coordinated AI stack. By pairing expansion goals with directives to integrate domestic chips and mainstream models, the policy positions hardware-software co-design as a lever for industry growth. The emphasis on model research alongside chip, memory, and interconnect technologies reflects a view that advances in algorithms and systems must move in step with the evolution of compute and data pathways.
This coupling of scale targets with architectural intent suggests that the path to 2030 runs through cohesive layers rather than siloed advances. The plan’s references to next-generation model architectures and world models point to continued evolution in how systems learn and generalize, while the inclusion of physical intelligence and brain-inspired intelligence places embodied and biologically inspired approaches on the research agenda.
Quantum intelligence is also named, aligning frontier exploration with the stated interest in QPU integration. Each of these areas implies different computational and memory access patterns, which the policy addresses by calling out specific chip categories, memory technology, and interconnect and packaging approaches.
A Full-Stack Path Across Chips, Memory, Interconnect, and Servers
A notable feature of the plan is its call for deeper integration of domestic chips with mainstream models across GPU and NPU, QPU, CPO, HBM, and heterogeneous servers. This is a full-stack signal. It points to the need for alignment between model architectures and the compute primitives available in different processors, while ensuring that memory and interconnect solutions can feed those processors efficiently. Heterogeneous servers, by definition, bring multiple processor types together, which raises opportunities for workload partitioning and model placement strategies that match different layers or stages of training and inference to the most suitable compute resources.
The inclusion of CPO and HBM indicates that interconnect density and memory bandwidth are treated as first-order concerns in the push to link domestic chips with mainstream models. This is consistent with the broader framing of the policy, which groups chips, models, interconnect, memory, and deployment into a single design space. By embedding these elements into one planning framework, the policy steers the ecosystem toward solutions where model performance characteristics are accounted for in server designs and cluster topologies. The research agenda around brain-inspired and physical intelligence adds dimension to this by anticipating the demands of new model classes that may stress different parts of the stack.
Tiered Compute Clusters Positioned as Planning Objectives
A research note from Guotai Haitong describes a tiered cluster program aligned with the plan’s direction. It reports 100,000-card clusters planned in Songjiang, Lingang, and Qingpu, complemented by thousand-card clusters and hundred-card edge facilities. These should be understood as planning targets rather than existing capacity, and the plan does not set a firm launch timetable for each tier. The cluster design as described offers a hierarchy that can map central workloads to the largest facilities while enabling regional or edge use cases at smaller scales. Details of this approach are covered in the Guotai Haitong research note.
Positioning large clusters in multiple districts as targets can help distribute planned compute while retaining the option to align facilities with local developer communities and application domains. Thousand-card clusters can serve as regional hubs for training and fine-tuning of mainstream models on domestic chips, while hundred-card edge facilities can align with latency-sensitive or localized workloads. When paired with heterogeneous servers and the memory and interconnect stack highlighted in the plan, this tiering provides a conceptual map for how different scales of compute might be orchestrated around the needs of evolving model architectures.
The policy’s naming of QPU, CPO, and HBM points to the breadth of the contemplated stack. QPU indicates that quantum-related interfaces are on the research horizon. CPO elevates the role of co-packaged connectivity between compute and optical links, which matters when models place heavy demands on inter-node communication. HBM is central to sustaining the bandwidth needs of models under training or serving. In combination with GPU and NPU and heterogeneous servers, these elements give the plan a concrete vocabulary for how to bind domestic chips with mainstream models and how to stage deployments across different facility sizes.
The research focus on next-generation model architectures intersects with the infrastructure emphasis in practical ways. Physical intelligence and brain-inspired intelligence may call for different data representations or sensor integrations, and world models may benefit from memory hierarchies that balance capacity and throughput. Integrating these considerations with server designs and cluster topology at the planning stage can reduce friction during later deployment. The plan’s language sets expectations that model and hardware teams will coordinate so that mainstream models can run effectively on domestic chips, backed by the specified memory and interconnect technologies.
As a policy instrument, the plan combines sector targets with a blueprint for how compute, memory, and interconnect should meet model requirements. By anchoring the strategy in both research and infrastructure planning, it lays out a path where software and information-services growth aligns with the evolution of the AI stack. The tiered clusters described as planning targets illustrate how deployment might scale, while the list of technologies and research domains set the agenda for what needs to be developed and integrated. The result is a roadmap where models, chips, interconnect, memory, and compute facilities are addressed in a single, interdependent framework.