The component that accounts for half the production cost of every advanced AI chip has become one of the most contested battlegrounds in the US-China technology rivalry. High-bandwidth memory , the stacked DRAM architecture that feeds data to AI processors at the speeds modern inference and training require , has emerged as a chokepoint that Washington moved to close in December 2024. What has followed suggests the controls came with significant gaps that Chinese industry is now moving to exploit from within.
Chinese chipmakers and outsourced semiconductor assembly and test firms, known as OSATs, are moving aggressively to fill those gaps. DigiTimes reported on May 20 that SMIC is returning to advanced packaging and that JCET, one of China’s largest packaging houses, is expanding its advanced packaging capacity. The activity reflects a broader strategic posture: build the domestic capability that import restrictions are meant to deny.
What HBM Actually Does and Why It Matters
HBM improves AI chip performance by stacking multiple DRAM dies vertically and connecting them through silicon vias, a technique that dramatically increases memory bandwidth while reducing the physical footprint of the combined memory-chip assembly. The HBM stack is then integrated with the processor on a shared silicon interposer, allowing data transfers that conventional DRAM cannot match.
That architecture is what makes HBM indispensable for large AI models. Training and inference workloads on transformer-based systems require moving enormous volumes of data between memory and compute in very short windows. Without HBM, the processor waits. The memory bottleneck becomes the AI bottleneck. This is why, according to analysis published by AI-Frontiers in February 2026, HBM accounts for approximately half of the production cost of a fully assembled AI chip, a figure that gives the component outsized strategic weight.
Three companies currently control 97% of global HBM wafer production: SK Hynix, Samsung, and Micron. All three are headquartered in US-allied countries and subject to Washington’s export licensing regime. The December 2024 restrictions were designed to sever China’s access to this supply.
The Gaps That Opened the Window
The restrictions did not close cleanly. The AI-Frontiers analysis identified two structural weaknesses in the control architecture. First, the rules left hybrid bonding equipment, a technique used to compress HBM stacks and extend their generational roadmap, outside the initial coverage. Second, the announcement-to-implementation gap gave Chinese buyers a usable window: Huawei and Baidu reportedly stockpiled approximately six million Samsung HBM stacks before the rules took effect and acquired an additional seven million in the month between the public announcement and the date the controls became enforceable.
CXMT, China’s leading DRAM manufacturer, has used that interval and the equipment it procured to advance domestic HBM development. The company is targeting HBM3 production, with estimates suggesting output capacity sufficient to supply roughly 600,000 AI chips annually in 2026. That number remains well below what Chinese AI labs require, and CXMT’s technology is several generations behind the HBM3e products SK Hynix now ships in volume. But the direction is unambiguous.
The domestic packaging effort matters in part because building HBM is not only about the DRAM dies themselves. Advanced packaging , integrating those dies with the processor on an interposer , is a separate technical challenge requiring specialized equipment, process knowledge, and yield management. SMIC’s return to this domain and JCET’s capacity expansion suggest Chinese industry is treating the full HBM supply chain, from die production to final assembly, as a domestic development priority. SMIC’s previous record revenue performance on the back of AI demand has given it both capital and motivation to invest in adjacent capabilities.
Multi-Patterning as a Workaround
Chinese firms face a technology constraint in their own memory fabs. Without access to extreme ultraviolet lithography, which remains controlled, CXMT is working with immersion DUV equipment and multi-patterning techniques to produce the fine features needed for advanced DRAM. Multi-patterning, exposing the same wafer layer multiple times at slightly different offsets, can achieve finer geometries with older tools, but it increases defect rates and slows throughput. The approach is workable at lower volumes, but scaling it to meet China’s AI industry demand is a different challenge.
That limitation is part of why the packaging ecosystem matters so much right now. Even if Chinese DRAM production remains constrained, improving the integration of available dies with domestic processors can extract more performance from the chips China can already make. The effort is complementary to the broader Huawei Ascend ecosystem push that has been accelerating across Chinese cloud infrastructure, as domestic AI stacks consolidate around Ascend compute.
A Race the Controls Did Not Stop
The memory packaging acceleration sits within a larger pattern: US export controls have significantly raised the cost and complexity of China’s AI hardware development, but have not halted it. CXMT’s recent financial results reflected a 1,688% profit surge as the company moved to capitalize on domestic AI demand for every grade of memory it can supply. The market incentives pushing Chinese firms toward HBM self-sufficiency are at least as strong as the policy incentives.
What the controls have done is buy time for US and allied chipmakers to extend their technology leads and for policymakers to design more comprehensive restrictions covering hybrid bonding and related equipment. Whether that time translates into a durable advantage depends on how quickly Chinese OSATs and memory producers can convert stockpiled equipment and acquired know-how into production yield. The DigiTimes reporting suggests that conversion is now underway at several sites simultaneously. The trajectory makes the next 18 months of CXMT output data one of the more consequential indicators in the global AI hardware competition.